ADZS-BF527-EZLITE【PDF 4/88 页】BOARD EVAL ADSP-BF527

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

regulator provides a range of core voltage levels when supplied

from V DDEXT . The voltage regulator can be bypassed at the user's

discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 , the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

ADDRESS ARITHMETIC UNIT

SP

I3

I2

L3

L2

B3

B2

M3

M2

FP

P5

I1

L1

B1

M1

DAG1

P4

DA1

DA0

32

32

I0

L0

B0

M0

DAG0

P3

P2

P1

P0

32

RAB

32

PREG

SD

LD1

LD0

32

32

32

R7.H

R7.L

32

32

ASTAT

SEQUENCER

R6.H

R6.L

R5.H

R4.H

R3.H

R2.H

R5.L

R4.L

R3.L

R2.L

8

16

8

8

16

8

ALIGN

DECODE

R1.H

R0.H

R1.L

R0.L

BARREL

SHIFTER

A0

40

40

40

40

A1

LOOP BUFFER

CONTROL

UNIT

32

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2 32 multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

Rev. D | Page 4 of 88 | July 2013

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